A memory system of a computer is one of major factors that affect the system architecture and software effectiveness. Major elements for evaluating performance of a system memory include access delay, bandwidth, and capacity. At present, with the rise of cloud computing and big data, the required data access capacity is increasingly higher.
FIG. 1 is a schematic structural diagram of a prior-art fully buffered dual in-line memory module. As shown in FIG. 1, in a fully buffered dual in-line memory module (Full Buffer Dual Inline Memory Module, FBDIMM for short) chip, an advanced memory buffer chip (Advanced Memory Buffer, AMB for short) is added to a dynamic random access memory (Dynamic Random-Access Memory, DRAM for short), or memory module. The AMB is connected to a memory controller, and therefore the memory module performs data interaction with the memory controller by using the AMB, and no longer performs a direct data interaction with the memory controller. In this mode for expanding a system memory, cascading between memory modules in the system is implemented by using the AMB chip, which increases access capacity of the system memory. Because AMB chips are connected in a series manner, connection between a memory module and another memory module is changed from traditional parallel connection to series connection. However, connection between memory chips inside a memory module is still parallel connection. Therefore, the AMB chip needs to convert series protocol to double data rate (Double Data Rate, DDR for short) for memory access instruction sent by the memory controller, which increases delay time of a memory access. In addition, because the AMB chips are connected in a series manner, a delay for accessing a relatively farther-away memory module is relatively high.